AMBA AHB FAQ

AMBA AHB - Arbitration
----------------------

1. When should a master assert and deassert the HLOCK signal for a locked
transfer?

The HLOCK signal must be asserted at least one cycle before the start of
the address phase of a locked transfer. This is required so that the
arbiter can sample the HLOCK signal as high at the start of the address
phase.

The master should deassert the HLOCK signal when the address phase of the
last transfer in the locked sequence has started.


2. Can an arbiter be designed to always allow bursts to complete?

A SPLIT, RETRY or ERROR response from a slave can always cause a burst to
be early terminated. This is outwith the control of the Arbiter and so must
be supported.

Undefined length INCR bursts cannot have their end point predicted, so
there is no efficient way that an Arbiter design can allow the burst to
complete before granting another master. INCR bursts must be arbitrated on
a cycle by cycle basis.

Defined length INCRx and WRAPx bursts can have their beats counted, and so
allowed to complete by the Arbiter. However because of the AHB arbitration
synchronous timing, there is no way to avoid possibly terminating a burst
immediately after the first transfer of the burst has been indicated.

The Arbiter only knows that a defined length burst is in progress by
sampling the HBURST bus. However the first point at which HBURST can be
sampled is after the first clock cycle of the first burst beat, by which
time the Arbiter may already have decided to grant another master and will
have changed the HGRANT outputs accordingly. Only a combinatorial path from
HBURST to HGRANT would allow the burst to be detected in time to avoid
early termination in this scenario, but combinatorial paths in the AHB bus
are not allowed. ask ARM


3. Why is HADDR sometimes shown as an input to the arbiter?

The address bus, HADDR, is not required as an input to the arbiter but in
some system designs it may be useful to use the address bus to determine a
good point to change over between bus masters. For example, the arbiter
could be designed to change bus ownership when a burst of transfers reaches
a quad word boundary.


4. When can the HGRANT signal change?

The HGRANT signal can change in any cycle and the following cases are
possible:

* It is possible that the HGRANT signal may be asserted and then removed
before the current transfer completes. This is acceptable because the
HGRANT signal is only sampled by masters when HREADY is high.

* A master can be granted the bus without requesting it.

* The above point also means that it is possible to be granted the bus in
the same cycle that it is requested. This can occur if the master is
coincidentally granted the bus in the same cycle that it requests it.


5. What is the relationship between the HLOCK signal and the HMASTLOCK
signal?

At the start of the address phase of every transfer the arbiter will sample
the HLOCK signal of the master that is about to start driving the address
bus and if HLOCK is asserted at this point then HMASTLOCK will be asserted
by the arbiter for the duration of the address phase of the transfer.


6. When should a master deassert its HBUSREQ signal?

For an undefined length burst (INCR) a master must keep its HBUSREQ signal
asserted until it has started the address phase of the last transfer in the
burst. This will mean that if the penultimate transfer in the burst is zero
wait state then the master may be granted the bus for an additional
transfer at the end of an undefined length burst.

For a defined length burst the master can deassert the HBUSREQ signal once
the master has been granted the bus for the first transfer. This can be
done because the arbiter is able to count the transfers in the burst and
keep the master granted until the burst completes.

However it is not a mandatory requirement for an Arbiter to allow a burst
to complete, so the master will have to re-assert HBUSREQ if the Arbiter
removes HGRANT before the burst has been completed.


7. When will the arbiter grant another master after a locked transfer?

The arbiter will always grant the master an extra transfer at the end of a
locked sequence, so the master is guaranteed to perform one transfer with
the HMASTLOCK signal low at the end of the locked sequence. This coincides
with the data phase of the last transfer in the locked sequence.

During this time the arbiter can change the HGRANT signals to a new bus
master, but if the data phase of the last locked transfer receives either a
SPLIT or RETRY response then the arbiter will drive the HGRANT signals to
ensure that either the master performing the locked sequence remains
granted on the bus for a RETRY response, or the Dummy master is granted the
bus for the SPLIT response.


8. Can a master deassert HLOCK during a burst?

The AHB specification requires that all address phase timed control signals
(other than HADDR and HTRANS) remain constant for the duration of a burst.

Although HLOCK is not an address phase timed signal, it does directly
control the HMASTLOCK signal which is address phase timed.

Therefore HLOCK must remain high for the duration of a burst, and can only
be deasserted such that the following HMASTLOCK signal changes after the
final address phase of the burst.


9. If a master is currently granted the bus by default, how many cycles before
starting an non-IDLE transfer does it have to assert HBUSREQ?

None. It can start a non IDLE transfer immediately.


10. Can a master perform transfers other than IDLE when the bus was granted to
it, but not requested by the master?

Yes. A master can perform transfers other than IDLE when it had not
requested the bus. Please note that in this case it is still recommended
that the master asserts its request signal so that the arbiter does not
change ownership of the bus to a lower priority master while the transfers
are in progress.

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AMBA 2 AHB - General
--------------------
1. The specification recommends that only 16 wait states are used. What should
you do if more than 16 cycles are needed?

For some slaves it is acceptable to insert more than 16 wait states. For
example, a serial boot ROM which is only ever accessed at initial power up
could insert a larger number of wait states and it would not affect the
calculation of the system performance and latency once system power up has
been completed.

For other slaves a number of options exist. A SPLIT or RETRY response could
be used to indicate that the slave is not yet able to perform the requested
data transfer, or the slave could be accessed either in response to
interrupts or after polling a status register, in either case indicating
that the slave is now able to respond in an acceptable number of cycles.


2. Why is a burst not allowed to cross a 1 kilobyte boundary?

If an AHB slave samples HSELx at the start of a burst transaction, it knows
it will be selected for the duration of the burst. Also, a slave which is
not selected at the start of a burst will know that it will not become
selected until a new burst is started.

1 kilobyte is the smallest area an AHB slave may occupy in the memory map.
Therefore, if a burst did cross a 1 kilobyte boundary, the access could
start accessing one slave at the beginning of the burst and then switch to
another on the boundary, which must not happen for the above reason.

The 1 kilobyte boundary has been chosen as it is large enough to allow
reasonable length bursts, but small enough that peripherals can be aligned
to the 1 kilobyte boundary without using up too much of the available
memory map.


3. Can an AHB master be connected directly to an AHB slave?

Any slave which does not use SPLIT responses can be connected directly to
an AHB master. If the slave does use SPLIT responses then a simplified
version of the arbiter is also required.

If an AHB master is connected directly to an AHB slave it is important to
ensure that the slave drives HREADY high during reset and that the select
signal HSEL for the slave is tied permanently high.


4. What is the state of the AHB signals during reset?

The specification states that during reset the bus signals should be at
valid levels. This simply means that the signals should be logic '0' or
'1', but not Hi-Z. The actual logic levels driven are left up to the
designer. HTRANS is the only signal specified during reset, with a
mandatory value of IDLE.

It is important that HREADY is high during reset. If all slaves in the
system drive HREADY high during reset then this will ensure that this is
the case. However, if slaves are used which do not drive HREADY high
during reset it should be ensured that a slave which does drive HREADY high
is selected at reset.


5. Can a BUSY transfer occur at the end of a burst?

A BUSY transfer can only occur at the end of an undefined length burst
(INCR). A BUSY transfer cannot occur at the end of a fixed length burst
(SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16).


6. What is a default slave?

If the memory map of a system does not define the full 4 gigabyte address
space then a default slave is required, which is selected when an access is
attempted to the empty areas of the memory map. The default slave should
use an OKAY response for IDLE/BUSY transfers and an ERROR response sequence
for NONSEQ/SEQ transfers.


7. Is a default slave really necessary?

If the entire 4 gigabyte address space is defined then a default slave is
not required. If, however, there are undefined areas in the memory map then
it is important to ensure that a spurious access to a non-existent address
location will not lock up the system. The functionality of the default
slave is extremely simple and it will often make sense to implement this
within the decoder.


8. Is a dummy master really necessary?

A dummy master is necessary in any system which has a slave that can give
SPLIT transfer responses. The dummy master is required so that something
can be granted the bus if all the other masters have received a SPLIT
response.

No logic is required for the dummy master and it can be implemented by
simply tying off the inputs to the master address/control multiplexer for
the dummy master position. The requirements for a dummy master are that
HTRANS is driven to IDLE, HLOCK is driven low, and all other master outputs
are driven to legal values.


9. Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a
burst?

Yes, the control signals must remain constant throughout the duration of a
burst.


10. What default state should be used for the HREADY and HRESP outputs from a
slave?

It is recommended that the default value for HREADY is high and the default
value for HRESP is OKAY. This combination ensures that the slave will
respond correctly to IDLE transfers to the slave, even if the slave is in
some form of power saving mode.


11. Is HREADY an input or an output from slaves?

An AHB slave must have the HREADY signal as both an input and an output.

HREADY is required as an output from a slave so that the slave can extend
the data phase of a transfer.

HREADY is also required as an input so that the slave can determine when
the previously selected slave has completed its final transfer and the
first data phase transfer for this slave is about to commence.

Each AHB Slave should have an HREADY output signal (conventionally named
HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The
output of this multiplexer is the global HREADY signal which is routed to
all masters on the AHB and is also fed back to all slaves as the HREADY
input.


12. How many masters can there be in an AHB system?

The AHB specification caters for up to 16 masters. However, allowing for a
dummy bus master means the maximum number of real bus masters is actually
15. By convention bus master number 0 is allocated to the dummy bus
master.


13. Can a master change the address/control signals during a waited transfer?

Yes. If the address/control signals are indicating an IDLE transfer then
the master can change to a real transfer (NONSEQ) when HREADY is low.

However, if a master is indicating a real transfer (NONSEQ or SEQ) then it
cannot cancel this during a waited transfer unless it receives a SPLIT,
RETRY or ERROR response.


14. When a master rebuilds a burst which has been terminated early are there
any limitations on how it rebuilds the burst?

The only limitation is that the master uses legal burst combinations to
rebuild the burst. For example, if a master was performing an 8 beat burst,
but had only completed 3 transfers before losing control of the bus, then
the remaining 5 transfers could be performed either by using a 1 beat
SINGLE burst followed by a 4 beat INCR4 burst, or it could be performed
using a 5 beat undefined length INCR burst.

For simplicity it is recommended that masters use INCR bursts to rebuild
the remaining transfers.


15. What is the recommended default value for HPROT?

Many bus masters will not be able to generate accurate protection
information and for these bus masters it is recommended that the HPROT
encoding shows, Non-cacheable, Non-bufferable, Privileged, Data Accesses
which corresponds to HPROT[3:0] = 4'b0011.


16. Do all slaves have to support the BUSY transfer type?

Yes. All slaves must support the BUSY transfer type to ensure they are
compatible with any bus master.


17. What system support is required if a slave can be powered down or have its
clock stopped?

If a slave access is attempted while that slave is in a power down state or
has had its clock stopped, you must ensure that an access will cause the
power/clock to be restored, or else configure the AHB decoder up to
redirect any such accesses to the dummy slave so that the system does not
hang forever when an access to the device is made when it is disabled.

Redirecting the access in this way will ensure that random "IDLE" addresses
are treated with the HREADY high and HRESP=OKAY default response, but real
accesses (NONSEQ or SEQ) will be detected with an ERROR response.


18. When can Early Burst Termination occur

Bursts can be early terminated either as a result of the Arbiter removing
the HGRANT to a master part way through a burst, or after a slave returns a
non-OKAY response to any beat of a burst. Note however that a master cannot
decide to terminate a defined length burst unless prompted to do so by the
Arbiter or Slave responses.

All AHB Masters, Slaves and Arbiters must be designed to support Early
Burst Termination.


19. Does the address have to be aligned, even for IDLE transfers?

Yes. The address should be aligned according to the transfer size (HSIZE)
even for IDLE transfers. This will prevent spurious warnings from bus
monitors used during simulation.


20. What is the difference between a dummy bus master and a default bus
master?

The term default bus master is used to describe the master that is granted
when none of the masters in the system are requesting access to the bus.
Usually the bus master which is most likely to request the bus is made the
default master.

The dummy bus master is a master which only performs IDLE transfers. It is
required in a system so the arbiter can grant a master which is guaranteed
not to perform any real transfers. The two cases when the arbiter would
need to do this are when a SPLIT response is given to a locked transfer and
when a SPLIT response is given and all other masters have already been
SPLIT.


21. Is it legal for a master to change HADDR when a transfer is extended?

If a master is indicating that it wants to do a NONSEQ, SEQ or BUSY
transfer then it cannot change the address during an extended transfer
(when HREADY is low) unless it receives an ERROR, RETRY or SPLIT response.
If the master is indicating that it wants to do an IDLE transfer then it
may change the address.


22. Can HTRANS change whilst HREADY is low?

In general, an AHB master should not change control signals whilst HREADY
is low. However it is allowable to change HTRANS in the following
conditions:

* HTRANS = IDLE
The AHB master is performing internal operations and has not yet
committed to a bus transfer. However during the AHB wait states (HREADY
low) the master may determine that a bus transfer is required and change
HTRANS on the next cycle to NONSEQ.

* HTRANS = BUSY
HTRANS is being used to give the master time to complete internal
operations, which may be entirely independent of HREADY (i.e. wait states
on the AHB). Therefore HTRANS can change on the next cycle to any legal
value, i.e. SEQ if the burst is to continue, IDLE if the burst has
completed, NONSEQ if a separate burst is to begin.

* HRESP = SPLIT/RETRY
As stated in the AHB specification, a master must assert IDLE on HTRANS
during the second cycle of the two-cycle SPLIT or RETRY slave response so
HTRANS will change value from the first cycle to the second cycle of the
response.

* HRESP = ERROR
The master is permitted to change HTRANS in reaction to an ERROR response
in the same way as in reaction to a SPLIT/RETRY response and cancel any
further beats in the current burst (even if HBURST is indicating a
defined-length burst). In this case HTRANS changes to IDLE on the second
cycle of the response. Alternatively, the master is permitted to continue
with the current transfers.


23. What are the different bursts used for?

Typically a master would use wrapping bursts for cache line fills where the
master wants to access the data it requires first and then it completes the
burst to fetch the remaining data it requires for the cache line fill.
Incrementing bursts are used by masters, such as DMA controllers, that are
filling a buffer in memory which may not be aligned to a particular address
boundary.


24. What sequences of transfers types (HTRANS) can occur on the bus?

The following examples show some of the sequences of HTRANS that can occur
on the bus:

A normal burst of four transfers followed by an IDLE.
N - S - S - S - I

A normal burst of four transfers which includes BUSY transfers.
N - S - B - S - B - S - I

A burst of four transfers followed by another burst.
N - S - S - S - N - S - S - S - I

A single transfer followed by a burst of four transfers.
N - N - S - S - S - I

A single transfer followed by an IDLE
N - I

An undefined length burst which concludes with a BUSY transfer.
N - B - S - B - S - B - I

An undefined length burst which concludes with a BUSY transfer and is followed
immediately by another burst.

N - B - S - B - S - B - N - S


25. How should AHB to APB bridges handle accesses that are not 32-bits?

The bridge should simply pass the entire 32-bit data bus through the
bridge. Please note that when transfers less than 32-bits are performed to
an APB slave it is important to ensure that the peripheral is located on
the appropriate bits of the APB data bus.

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AHB - Split/Retry
-----------------

1. What value should be used for HTRANS when an AHB master gets a RETRY
response from a slave in the middle of burst?

Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it
may also be necessary to adjust the HBURST information (usually just to
indicate INCR).


2. What address should be on the bus during the IDLE cycle after a SPLIT or
RETRY?

It does not matter what address is driven onto the bus during this cycle.
The slave selected by the driven address should not take any action and
must respond with a zero wait state OKAY response.

In many cases it will be simpler for the master to leave the address
unaltered during this cycle, so that it remains at the address of the next
transfer that the master wishes to perform and only in the following cycle
does the master return the address to that of the transfer that must be
repeated because of the SPLIT or RETRY response.

In some designs it may be possible for the master to return the address to
that required to repeat the previous transfer during the IDLE cycle and
this behaviour is also perfectly acceptable.

3. Do all masters have to support SPLIT and RETRY?

Yes. All masters must support SPLIT and RETRY responses to ensure they are
compatible with any bus slave. A master will handle both SPLIT and RETRY
responses in an identical manner.


4. Can a SPLIT or RETRY response be given at any point during a burst?

Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any
transfer during a burst. The slave is not restricted to only giving these
responses to the first transfer.


5. Will a master always lose the bus after a SPLIT response?

Yes. A slave must not assert the relevant bit of the HSPLIT bus in the same
cycle that it gives the SPLIT response and therefore the master will always
lose the bus.


6. Can a slave assert HSPLITx in the same cycle that it gives a SPLIT
response?

No. The specification requires that HSPLITx can only be asserted after the
slave has given a SPLIT response.


7. Do all slaves have to support the SPLIT and RETRY responses?

No. A slave is only required to support the response types that it needs to
use. For example, a simple on-chip memory block which can respond to all
transfers in just a few wait states does not need to use either the SPLIT
or RETRY responses.


8. Can a slave use both SPLIT and RETRY responses?

Normally a slave will not use both the SPLIT and RETRY responses. The SPLIT
response should be used by any slave that may be accessed by many different
masters at the same time. The RETRY response is intended to be used by
peripherals that are only accessed by one bus master.


9. What is the difference between SPLIT and RETRY responses?

Both the Split and Retry responses are used by slaves which require a large
number of cycles to complete a transfer. These responses allow a data phase
transfer to appear completed to avoid stalling the bus, but at the same
time indicate that the transfer should be re-attempted when the master is
next granted the bus.

The difference between them is that a SPLIT response tells the Arbiter to
give priority to all other masters until the SPLIT transfer can be
completed (effectively ignoring all further requests from this master until
the SPLIT slave indicates it can complete the SPLIT transfer), whereas the
RETRY response only tells the Arbiter to give priority to higher priority
masters.

A SPLIT response is more complicated to implement than a RETRY, but has the
advantage that it allows the maximum efficiency to be made of the bus
bandwidth.

The master behaviour is identical to both SPLIT and RETRY responses, the
master has to cancel the next access and re-attempt the current failed
access.

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AMBA 2 APB - General
--------------------
1. Why is there no wait signal on the APB?

The APB has been designed to implement as simple an interface as possible.
Having this simple design makes it much easier to connect new APB
peripherals and makes the analysis of the system performance easier to
calculate.

Although many APB peripherals are slow devices, such as UARTs, they are
normally accessed via control registers. Typically the driver software will
first access a status register to determine that data is available and only
then access the data register. Both of these accesses are possible without
the addition of wait states and therefore the peripheral can easily be
accessed as an APB device.

Peripherals which do require wait states can be designed as AHB slaves and
in the rare case that a design does include a large number of these
peripherals then a secondary stub AHB can be used to reduce the loading on
the main system bus.


2. How should AHB to APB bridges handle accesses that are not 32-bits?

The bridge should simply pass the entire 32-bit data bus through the
bridge. Please note that when transfers less than 32-bits are performed to
an APB slave it is important to ensure that the peripheral is located on
the appropriate bits of the APB data bus
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