FPGA Design tips

1. Reduce clock skew
2. Clock dividers
3. Avoid glitches on clocks and asynchronous set/reset signals
4. The Global Set/Reset network
5. Select a state machine encoding scheme
6. Access carry logic
7. Build efficient counters

Why Synchronous Design?

1.Synchronous circuits are more reliable
2.Events are triggered by clock edges which occur at welldefined
intervals
3. Outputs from one logic stage have a full clock cycle to
propagate to the next stage
4. Skew between data arrival times is tolerated within the same
clock period
5 .Asynchronous circuits are less reliable
6 .A delay may need to be a specific amount (e.g. 12ns)
7. Multiple delays may need to hold a specific relationship (e.g.
 DATA arrives 5ns before SELECT)